# FPGA IP Design and Verification Engineer at Altera

- Company: Altera
- What the company does: Backed by a16z.
- Company website: https://www.altera.com
- Type: Startups
- Level: Mid level
- Location: Regus, Madhapur
- Work setup: On-site
- Posted: 2026-09-21
- Apply by: 2026-11-05
- Apply: https://altera.wd1.myworkdayjobs.com/en-US/Altera/job/Regus-Madhapur/FPGA-IP-Design-and-Verification-Engineer_R02945
- Page: https://www.1752.vc/careers/jobs/altera-fpga-ip-design-and-verification-engineer/

## About the role

Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment.

## What they're looking for

- 7+ years of experience in Semiconductor IP Design verification
- Familiarity with HDL languages (VHDL, Verilog, SystemVerilog )
- Experience or knowledge in scripting languages such as Tcl , Perl, or Python
- Prior experience or exposure to FPGA tools (Quartus or Vivado ) would be advantageous
- Strong willingness to learn new skills and technologies
- Ability to work collaboratively within a team environment