# Full Chip Timing Modeling and Integration Engineer at Altera

- Company: Altera
- What the company does: Backed by a16z.
- Company website: https://www.altera.com
- Type: Startups
- Level: Mid level
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $133K to $193K base salary per year (USD)
- Posted: 2026-10-10
- Apply by: 2026-11-24
- Apply: https://altera.wd1.myworkdayjobs.com/en-US/Altera/job/San-Jose-California-United-States/Full-Chip-Timing-Modeling-and-Integration-Engineer_R03228?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/altera-full-chip-timing-modeling-and-integration-engineer/

## About the role

Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers. As a Full Chip Timing Modeling and Integration Engineer , you will develop timing methodologies and execute full-chip timing for Altera’s next-generation product lines using the world's most advanced process technologies. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience in SoC development
- 5+ years of industry experience working with advanced semiconductor process nodes
- 5+ years of industry experience with industry-standard timing formats and design constraints, including Liberty, Verilog, and Synopsys Design Constraints (SDC)
- 5+ years of industry experience with Static Timing Analysis (STA), including correlating STA results with SPICE
- 5+ years of industry experience in timing modeling and library quality assurance (QA)
- 5+ years of industry experience writing Python and Tcl scripts for design automation


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/altera-full-chip-timing-modeling-and-integration-engineer/