# Senior Debug Verification Engineer at Altera

- Company: Altera
- What the company does: Backed by a16z.
- Company website: https://www.altera.com
- Type: Startups
- Level: Senior
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $149K to $215K base salary per year (USD)
- Posted: 2026-09-29
- Apply by: 2026-11-13
- Apply: https://altera.wd1.myworkdayjobs.com/en-US/Altera/job/San-Jose-California-United-States/Senior-Debug-Verification-Engineer_R03260?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/altera-senior-debug-verification-engineer/

## About the role

As a Sr. Debug Design Verification Engineer , you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- 8+ years of experience with complex ASIC designs and/or verification
- 8+ years of experience with SystemVerilog language
- 8+ years of experience on UVM verification methodology, and formal verification method
- 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable
- Strong communication skills and the ability to work with a team spread across different geography sites


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/altera-senior-debug-verification-engineer/