# Member of Technical Staff - Physical Design at Architect

- Company: Architect
- What the company does: Architect gives traders customizable infrastructure that reimagines access to international markets for digital assets. Backed by Cyber Fund.
- Company website: https://architect.co
- Type: Startups
- Level: Senior
- Location: Palo Alto
- Work setup: On-site
- Posted: 2026-09-14
- Apply by: 2026-10-29
- Apply: https://jobs.ashbyhq.com/architect/2e0d4877-52cd-4142-9413-9349545c0870
- Page: https://www.1752.vc/careers/jobs/architect-member-of-technical-staff-physical-design/

## About the role

As our first Physical Design engineer, you'll build the PD function from scratch and extend our AI system from spec-to-netlist to tapeout-ready GDS. You'll own the methodology and hands-on execution for physical implementation at 3nm, 2nm, and future leading-edge nodes. Build the methodology: Establish and qualify the complete netlist-to-GDS flow, including PDKs, libraries, tools, constraints, automation, and reproducible regression infrastructure.

## What they're looking for

- Tapeout ownership: Multiple production tapeouts, with direct physical implementation and signoff responsibility at 3nm or 2nm and experience leading full-chip closure
- Methodology development: A track record of building production PD methodology from scratch for advanced nodes, including PDK/library qualification, tool evaluation, and deployment across chip programs
- Technical depth: Deep expertise in hierarchical implementation, multi-mode multi-corner timing analysis, variation, clocking, congestion, low-power design, extraction, and power integrity
- EDA expertise: Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus, along with commercial timing, extraction, power integrity, and physical verification tools
- Automation: Strong Tcl and Python skills, with experience building maintainable flow scripts, automated checks, regressions, and actionable PPA reporting
- Technical leadership: Ability to independently establish the flow, debug difficult closure problems, and explain implementation trade-offs to hardware, software, and AI teams

Tags: ASIC