# Design Verification Tech Lead- SerDes/PHY IP at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Senior
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $160K to $200K base salary per year (USD)
- Posted: 2026-09-21
- Apply by: 2026-11-05
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4733710005
- Page: https://www.1752.vc/careers/jobs/astera-labs-design-verification-tech-lead-serdes-phy-ip/

## About the role

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.

## What they're looking for

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
- Expert-level proficiency in SystemVerilog and UVM
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL

Tags: Design Verification SCE