# Manager, Digital Design at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Senior
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $216K to $240K base salary per year (USD)
- Posted: 2026-09-17
- Apply by: 2026-11-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4727604005
- Page: https://www.1752.vc/careers/jobs/astera-labs-manager-digital-design/

## About the role

As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.

## What they're looking for

- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field
- Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations
- 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design
- Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity
- Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality
- Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations

Tags: Silicon Engineering CCE1