# Physical Design Engineering, VP at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Principal and up
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $251K to $375K base salary per year (USD)
- Posted: 2026-07-27
- Apply by: 2026-10-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4686914005
- Page: https://www.1752.vc/careers/jobs/astera-labs-physical-design-engineering-vp/

## About the role

Astera Labs is seeking a VP of Physical Design to lead our critical full-chip physical design efforts for next-generation switching products featuring UCIe and UALink technologies. This strategic leadership role will drive the physical implementation of highly complex, multi-die chiplet architectures that are essential to enabling rack-scale AI infrastructure.

## What they're looking for

- Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity
- Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs
- Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces
- Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects
- Scale and develop a world-class physical design organization to support aggressive product roadmap
- Manage and mentor Directors, Managers, and senior engineers across the physical design team

Tags: ASIC Engineering