# Principal PCS/PMA RTL Design Engineer at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Principal and up
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $185K to $240K base salary per year (USD)
- Posted: 2026-11-03
- Apply by: 2026-12-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4733832005?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/astera-labs-principal-pcs-pma-rtl-design-engineer/

## About the role

Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- Master's degree is preferred
- 3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience
- Hands-on experience with Verilog or SystemVerilog RTL development
- Understanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces
- Working knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer

Tags: SerDes

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/astera-labs-principal-pcs-pma-rtl-design-engineer/