# Principal Physical Design Engineer -EMIR & Power Integrity at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Principal and up
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $185K to $240K base salary per year (USD)
- Posted: 2026-07-22
- Apply by: 2026-10-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4693897005
- Page: https://www.1752.vc/careers/jobs/astera-labs-principal-physical-design-engineer-emir-and-power-integrity/

## About the role

Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Principal Physical Design Engineer , you will own IR drop and electromigration (EMIR) analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.

## What they're looking for

- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below)
- Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria
- Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX
- Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis

Tags: ASIC Engineering