# Principal Physical Design Engineer, Methodology at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Principal and up
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $185K to $240K base salary per year (USD)
- Posted: 2026-07-22
- Apply by: 2026-10-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4692163005
- Page: https://www.1752.vc/careers/jobs/astera-labs-principal-physical-design-engineer-methodology/

## About the role

Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage

## What they're looking for

- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, Masters Preferred
- 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
- Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
- Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains
- Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation
- Experience building and maintaining multi-corner/multi-mode analysis infrastructure

Tags: ASIC Engineering