# Principal Verification Engineer at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Principal and up
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $185K to $230K base salary per year (USD)
- Posted: 2026-09-29
- Apply by: 2026-11-13
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4738838005?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/astera-labs-principal-verification-engineer/

## About the role

Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Bachelor’s degree in Electrical Engineering (Master’s preferred)
- 8+ years of experience in SoC verification, particularly for server and networking applications
- Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle
- Proficiency with industry-standard simulators, version control, and regression systems
- Strong debugging and coverage analysis skills
- Experience developing and executing test sequences, generating stimuli, and identifying verification holes

Tags: ASIC Engineering

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/astera-labs-principal-verification-engineer/