# Senior Design Verification Engineer at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Senior
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $149K to $165K base salary per year (USD)
- Posted: 2026-09-28
- Apply by: 2026-11-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4738049005?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/astera-labs-senior-design-verification-engineer/

## About the role

As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Verification Strategy and Planning
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality
- Review designs and verification plans with architecture and RTL teams to identify corner cases early
- Environment Development and Execution
- Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models

Tags: Design Verification CCE2

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/astera-labs-senior-design-verification-engineer/