# Synthesis & STA Engineer – High-Speed SerDes at Astera Labs

- Company: Astera Labs
- What the company does: Astera Labs: Purpose-Built Connectivity for Rack-Scale AI.
- Company website: https://www.asteralabs.com
- Type: Startups
- Level: Mid level
- Location: San Jose, California, United States
- Work setup: On-site
- Pay: $160K to $200K base salary per year (USD)
- Posted: 2026-10-27
- Apply by: 2026-12-11
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4748148005?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/astera-labs-synthesis-and-sta-engineer-high-speed-serdes-2/

## About the role

As an Astera Labs Synthesis & STA Engineer – High-Speed SerDes you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Bachelor's in Electrical Engineering or Computer Science required, Master's preferred
- ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications
- Strong proficiency in writing and debugging SDC constraints , with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling
- Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below)
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains

Tags: SerDes

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/astera-labs-synthesis-and-sta-engineer-high-speed-serdes-2/