# DFT Lead Engineer at Broadcom

- Company: Broadcom
- What the company does: Broadcom delivers semiconductors and infrastructure software for global enterprises’ most complex, mission-critical needs.
- Company website: https://www.broadcom.com
- Type: Startups
- Level: Senior
- Location: USA-CA San Jose Innovation Drive
- Work setup: On-site
- Posted: 2026-11-03
- Apply by: 2026-12-18
- Apply: https://broadcom.wd1.myworkdayjobs.com/en-US/external_career/job/USA-CA-San-Jose-Innovation-Drive/DFT-Lead-Engineer_R027685?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/broadcom-dft-lead-engineer/

## About the role

Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
- Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
- Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/broadcom-dft-lead-engineer/