# RTL2GDS IC Design Engineer Architect at Cadence

- Company: Cadence
- What the company does: Cadence delivers remote patient monitoring and chronic disease management that improves outcomes and reduces cost at scale. Intelligent senior care that works better by working ahead. Backed by General Catalyst.
- Company website: https://www.cadence.care/
- Type: Startups
- Level: Mid level
- Location: SAN JOSE
- Work setup: On-site
- Pay: $186K to $345K base salary per year (USD)
- Posted: 2026-11-05
- Apply by: 2026-12-20
- Apply: https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/job/SAN-JOSE/RTL2GDS-IC-Sr-Principal-Design-Engineer_R55850?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/cadence-rtl2gds-ic-design-engineer-architect/

## About the role

◦ Provide technical support to Cadence customers in Digital Design Implementation and Signoff, including synthesis, floorplanning, placement, clock tree synthesis, routing, design closure, static timing analysis, power integrity, and timing/power signoff. ◦ Lead block, subsystem, or full-chip RTL-to-GDS implementation from synthesized RTL or netlist through final GDS and design-database handoff. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Requires a BS, MS, or PhD in Electrical Engineering or a related field, with 15–17 years of industry experience in design and EDA, focused on Digital Implementation and Signoff
- Deep understanding of the ASIC RTL-to-GDS implementation process and signoff requirements
- Strong hands-on experience with Place and Route tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler
- Experience with synthesis tools such as Cadence Genus or RTL Compiler, or Synopsys Design Compiler
- Experience with EDA tools used in IC digital implementation and signoff flows, including STA tools such as Cadence Tempus or Synopsys PrimeTime
- Strong STA and SDC debugging abilities are required, including MMMC analysis, timing exceptions, OCV-based analysis, clock modeling, SI effects, and implementation-to-signoff correlation


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/cadence-rtl2gds-ic-design-engineer-architect/