# ASIC DFT Engineer - Acacia (Hybrid) at Cisco

- Company: Cisco
- What the company does: Cisco is a worldwide technology leader powering an inclusive future for all. Learn more about our products, services, solutions, and innovations. Backed by Sequoia and Menlo.
- Company website: https://www.cisco.com/
- Type: Startups
- Level: Mid level
- Location: San Jose, California, US
- Work setup: On-site
- Posted: 2026-10-27
- Apply by: 2026-12-11
- Apply: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-Engineer---Acacia--Hybrid-_2029368-1?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/cisco-asic-dft-engineer-acacia-hybrid/

## About the role

We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience
- Experience with ASIC DFT implementation or validation
- Experience with industry DFT tools such as Siemens Tessent , Synopsys DFT Compiler/TestMAX , or equivalent
- Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
- Experience with stuck-at and transition fault models
- Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/cisco-asic-dft-engineer-acacia-hybrid/