# ASIC DFT Technical Leader at Cisco

- Company: Cisco
- What the company does: Cisco is a worldwide technology leader powering an inclusive future for all. Learn more about our products, services, solutions, and innovations. Backed by Sequoia and Menlo.
- Company website: https://www.cisco.com/
- Type: Startups
- Level: Mid level
- Location: San Jose, California, US
- Work setup: On-site
- Posted: 2026-09-16
- Apply by: 2026-10-31
- Apply: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-Technical-Leader_2025666
- Page: https://www.1752.vc/careers/jobs/cisco-asic-dft-technical-leader/

## About the role

You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips.

## What they're looking for

- Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 12+ years of experience
- Prior experience in post-silicon debug experience from first silicon to production
- Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Prior experience working with Gate level simulation, debugging with VCS and other simulators