# ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid) at Cisco

- Company: Cisco
- What the company does: Cisco is a worldwide technology leader powering an inclusive future for all. Learn more about our products, services, solutions, and innovations. Backed by Sequoia and Menlo.
- Company website: https://www.cisco.com/
- Type: Startups
- Level: Mid level
- Location: San Jose, California, US
- Work setup: On-site
- Posted: 2026-10-21
- Apply by: 2026-12-05
- Apply: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Packaging-Signal-Power-Integrity-Hardware-Engineer--Hybrid-_2029221-1?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/cisco-asic-packaging-signal-power-integrity-hardware-engineer-hybrid-3/

## About the role

This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
- Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation
- Circuit Analysis: Experience with SPICE for circuit-level analysis, signal modeling, and performance validation


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/cisco-asic-packaging-signal-power-integrity-hardware-engineer-hybrid-3/