# Staff Analog Design Engineer at d-Matrix

- Company: d-Matrix
- What the company does: d-Matrix is redefining AI inference with memory-centric compute built for ultra-low latency, greater efficiency, and scalable AI infrastructure.
- Company website: https://www.d-matrix.ai
- Type: Startups (AI role)
- Level: Senior
- Location: Santa Clara
- Work setup: Remote
- Pay: $155K to $250K base salary per year (USD)
- Posted: 2025-05-20
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/d-Matrix/baf4903f-0fff-4ad2-aa2b-8a56b104db5c
- Page: https://www.1752.vc/careers/jobs/d-matrix-staff-analog-design-engineer/

## About the role

d-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out.

## What they're looking for

- We'd be excited about candidates with deep expertise in any one of the following areas:
- SerDes verification & characterization — building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)
- Clocking & CDR — ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architectures
- TX/RX datapath — high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architectures
- Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participation

Tags: Hardware Engineering