# Lead Digital Verification Engineer at Efficient Computer

- Company: Efficient Computer
- What the company does: Efficient Computer builds the world's most energy-efficient general-purpose AI chips, delivering up to 100× better efficiency than low-power CPUs. Backed by USV.
- Company website: https://www.efficient.computer/
- Type: Startups
- Level: Senior
- Location: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
- Work setup: On-site
- Pay: $200K to $260K base salary per year (USD)
- Posted: 2026-02-18
- Apply by: 2026-10-08
- Apply: https://job-boards.greenhouse.io/efficientcomputer/jobs/4137172009
- Page: https://www.1752.vc/careers/jobs/efficient-computer-lead-digital-verification-engineer/

## About the role

We are looking for an experienced Design Verification Lead to drive the functional verification of complex SoC/IP designs from specification through tapeout in a newly formed hardware engineering organization. You will own the verification strategy, define methodology standards, build and guide a team of verification engineers, and serve as the final authority on verification quality and sign-off readiness.

## What they're looking for

- Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
- Experience: 10+ years of progressive experience in ASIC/SoC design verification, with at least 3 years in a lead role owning verification strategy, sign-off, and team execution
- UVM Mastery: Deep expertise in UVM-based testbench architecture and constrained-random verification methodology — not just usage, but architectural decision-making and optimization
- SystemVerilog: Advanced proficiency in SystemVerilog for verification including classes, constraints, functional coverage, assertions (SVA), interfaces, and packages
- Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs
- Debug Skills: Proven ability to debug deeply complex simulation failures spanning multiple design blocks, protocols, and abstraction levels

Tags: Verification & Emulation