# Lead RTL Design Engineer at Efficient Computer

- Company: Efficient Computer
- What the company does: Efficient Computer builds the world's most energy-efficient general-purpose AI chips, delivering up to 100× better efficiency than low-power CPUs. Backed by USV.
- Company website: https://www.efficient.computer/
- Type: Startups
- Level: Senior
- Location: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
- Work setup: On-site
- Pay: $200K to $275K base salary per year (USD)
- Posted: 2026-04-30
- Apply by: 2026-10-08
- Apply: https://job-boards.greenhouse.io/efficientcomputer/jobs/4236891009
- Page: https://www.1752.vc/careers/jobs/efficient-computer-lead-rtl-design-engineer/

## About the role

Specifications, Documentations and Reviews: Author and own uArch specification documents for assigned blocks; drive design reviews with architecture, compiler, DV, and physical design stakeholders.

## What they're looking for

- 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC
- Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware, able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch
- Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures, familiarity with the hardware challenges of token-based firing-rule evaluation and producer-consumer synchronization
- Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces
- Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic
- Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level

Tags: Digital Design