# Physical Design - SOC Top Lead at Efficient Computer

- Company: Efficient Computer
- What the company does: Efficient Computer builds the world's most energy-efficient general-purpose AI chips, delivering up to 100× better efficiency than low-power CPUs. Backed by USV.
- Company website: https://www.efficient.computer/
- Type: Startups
- Level: Senior
- Location: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
- Work setup: On-site
- Pay: $180K to $260K base salary per year (USD)
- Posted: 2026-08-03
- Apply by: 2026-10-08
- Apply: https://job-boards.greenhouse.io/efficientcomputer/jobs/4343792009
- Page: https://www.1752.vc/careers/jobs/efficient-computer-physical-design-soc-top-lead/

## About the role

We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team.

## What they're looking for

- Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
- 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level (not just block-level)
- Deep hands-on experience with advanced nodes
- Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
- Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
- Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)

Tags: Physical Design