# Senior Digital Verification Engineer at Efficient Computer

- Company: Efficient Computer
- What the company does: Efficient Computer builds the world's most energy-efficient general-purpose AI chips, delivering up to 100× better efficiency than low-power CPUs. Backed by USV.
- Company website: https://www.efficient.computer/
- Type: Startups
- Level: Senior
- Location: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
- Work setup: On-site
- Pay: $160K to $245K base salary per year (USD)
- Posted: 2026-09-01
- Apply by: 2026-10-16
- Apply: https://job-boards.greenhouse.io/efficientcomputer/jobs/4391770009
- Page: https://www.1752.vc/careers/jobs/efficient-computer-senior-digital-verification-engineer/

## About the role

We are looking for an experienced Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

## What they're looking for

- Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field
- Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout
- UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
- C/C++ experience for modelling or verification
- Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs
- Debug Skills: Proven ability to debug complex simulation failures

Tags: Verification & Emulation