# Advanced Packaging SI/PI Engineer at Etched

- Company: Etched
- What the company does: Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
- Company website: https://www.etched.com/
- Type: Startups
- Level: Mid level
- Location: San Jose
- Work setup: On-site
- Pay: $150K to $275K base salary per year (USD)
- Posted: 2026-08-27
- Apply by: 2026-10-11
- Apply: https://jobs.ashbyhq.com/etched/5c3d84b0-0d6a-430b-80b5-f378eb541202
- Page: https://www.1752.vc/careers/jobs/etched-advanced-packaging-si-pi-engineer/

## About the role

As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. The ideal candidate will have extensive experience with high-power package and board designs, robust power delivery networks, and high-speed signaling solutions in advanced packaging. You will work closely with silicon, package, platform, and system teams to co-design world-class platforms with OSAT and ODM partners.

## What they're looking for

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals
- 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms
- Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis
- Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces
- Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS
- Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs

Tags: Architecture