# Formal Verification - DV at Etched

- Company: Etched
- What the company does: Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
- Company website: https://www.etched.com/
- Type: Startups
- Level: Mid level
- Location: San Jose
- Work setup: On-site
- Posted: 2026-06-10
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/etched/07b00790-2817-4863-a330-b0caf2322460
- Page: https://www.1752.vc/careers/jobs/etched-formal-verification-dv/

## About the role

We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers.

## What they're looking for

- 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon
- Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology
- Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
- Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces
- Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models
- Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports

Tags: ASIC