# Physical Design Engineer - Block Level, Subsystem Implementation at Etched

- Company: Etched
- What the company does: Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
- Company website: https://www.etched.com/
- Type: Startups
- Level: Mid level
- Location: Austin
- Work setup: On-site
- Pay: $200K to $300K base salary per year (USD)
- Posted: 2026-07-30
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/etched/127f9760-3069-4152-b882-4e76b8f4ff1d
- Page: https://www.1752.vc/careers/jobs/etched-physical-design-engineer-block-level-subsystem-implementation/

## About the role

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.

## What they're looking for

- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis

Tags: ASIC