# Physical Design Engineer - Flow & Methodologies at Etched

- Company: Etched
- What the company does: Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
- Company website: https://www.etched.com/
- Type: Startups
- Level: Mid level
- Location: San Jose
- Work setup: On-site
- Pay: $200K to $300K base salary per year (USD)
- Posted: 2026-07-23
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/etched/d8ee2a43-d5be-47f0-9c89-f7a39bb9db0d
- Page: https://www.1752.vc/careers/jobs/etched-physical-design-engineer-flow-and-methodologies/

## About the role

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Methodology Engineer, you will architect our PD flow from first principles. You will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies. Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff handoff.

## What they're looking for

- 5-10+ years of previous experience with PD or PD methodology/CAD
- Experience building and owning automated RTL-to-GDSII flows used by multiple block owners
- Experience creating block level and full chip level PG mesh from scratch, including interpretation of design rule documents and EM/IR analysis
- Experience with DRC-clean floorplanning flows and automated checks
- Experience with Cadence (Innovus, Genus) or Synopsys ( Fusion Compiler) automated RTL-to-GDSII flows
- Experience with PPA tuning and timing correlation across pre-route, post-route, and signoff environments

Tags: ASIC