# Physical Design Engineer - Full Chip Implementation at Etched

- Company: Etched
- What the company does: Co-designed chips, racks, and software to push the pareto frontier to best-in-class throughput and interactivity. Backed by Kleiner Perkins and Sequoia.
- Company website: https://www.etched.com/
- Type: Startups
- Level: Mid level
- Location: San Jose
- Work setup: On-site
- Pay: $200K to $300K base salary per year (USD)
- Posted: 2026-07-23
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/etched/045b3672-d7b7-48b5-95e5-3f8793ff819b
- Page: https://www.1752.vc/careers/jobs/etched-physical-design-engineer-full-chip-implementation/

## About the role

Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs—from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure.

## What they're looking for

- 10+ years of previous experience with chip planning, top level PD, floorplanning
- Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
- Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
- Experience with Pegasus or Calibre for physical verification signoff
- Experience with hierarchical timing budgeting, constraint management, and ECO closure

Tags: ASIC