# Quantum PDK Design Enablement Engineer at GlobalFoundries

- Company: GlobalFoundries
- Company website: https://selfservice.globalfoundries.com
- Type: Startups
- Level: Mid level
- Location: 2 Locations
- Work setup: On-site
- Posted: 2026-09-28
- Apply by: 2026-11-12
- Apply: https://globalfoundries.wd1.myworkdayjobs.com/en-US/External/job/USA---New-York---Malta/Quantum-PDK-Design-Enablement-Engineer_JR-2605677
- Page: https://www.1752.vc/careers/jobs/globalfoundries-quantum-pdk-design-enablement-engineer/

## About the role

The Design Enablement Engineer, DRC/LVS/PEX is responsible for developing, qualifying, and deploying physical verification and parasitic extraction components for semiconductor Process Design Kits (PDKs). The role translates complex process and design requirements into accurate, robust, and efficient DRC, LVS, and PEX rule decks and verification flows, while advancing automation and AI/ML-assisted methodologies to improve PDK quality, development efficiency, and customer design success.

## What they're looking for

- Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field
- Experience: Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level
- Physical Verification: Experience with DRC and/or LVS rule development, coding, debug, or qualification
- PEX: Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance
- Semiconductor Technology: Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions
- EDA: Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies