# TPU RTL Design Engineer, Networking, Inter-Chip Interconnects at Google

- Company: Google
- What the company does: Learn more about Google. Explore our innovative AI products and services, and how we. Backed by Kleiner Perkins.
- Company website: https://about.google/
- Type: Startups
- Level: Mid level
- Location: United States
- Work setup: On-site
- Posted: 2026-09-21
- Apply by: 2026-11-05
- Apply: https://www.google.com/about/careers/applications/jobs/results/107404549483832006-tpu-rtl-design-engineer-networking-interchip-interconnects
- Page: https://www.1752.vc/careers/jobs/google-tpu-rtl-design-engineer-networking-inter-chip-interconnects/

## About the role

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.

## What they're looking for

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 4 years of experience in high-performance ASIC design
- Experience architecting or designing RTL solutions for digital systems
- Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers
- Experience with high-speed interconnects