# IC/RTL Design Engineer at Lumilens

- Company: Lumilens
- What the company does: Backed by Redpoint.
- Company website: https://lumilens.com/
- Type: Startups
- Level: Mid level
- Location: San Jose
- Work setup: On-site
- Posted: 2026-07-06
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/lumilens/d11f8288-3a49-402a-b32a-b7d6f7d605e5
- Page: https://www.1752.vc/careers/jobs/lumilens-ic-rtl-design-engineer/

## About the role

Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions. Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.

## What they're looking for

- BS or MS in Electrical/Computer Engineering (or equivalent experience)
- 3+ years of digital RTL design in SystemVerilog , with blocks taken from micro-architecture through to verification handoff
- Solid digital design fundamentals : pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI)
- Lint and CDC/RDC discipline and clean-RTL practices
- Power- and timing-aware design practices, comfort with synthesis and timing closure, working with the backend team
- Strong debug skills in simulation , scripting in Python, Perl, or TCL

Tags: Engineering