# Senior Principal Engineer – Hardware Chip Lead, Connectivity BU at Marvell Technology

- Company: Marvell Technology
- What the company does: Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
- Company website: https://www.marvell.com
- Type: Startups
- Level: Principal and up
- Location: Santa Clara, CA
- Work setup: On-site
- Posted: 2026-09-25
- Apply by: 2026-11-09
- Apply: https://marvell.wd1.myworkdayjobs.com/en-US/marvellcareers/job/Santa-Clara-CA/Senior-Principal-Engineer---Hardware-Chip-Lead--Connectivity-BU_2602772
- Page: https://www.1752.vc/careers/jobs/marvell-technology-senior-principal-engineer-hardware-chip-lead-connectivity-bu/

## About the role

Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane.

## What they're looking for

- · Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 15+ years of related professional experience
- · OR Master’s degree in Electrical Engineering, Computer Engineering, or related field with 10–12 years of experience
- · OR PhD in Electrical Engineering, Computer Engineering, or related field with 8–10 years of experience
- · Proven track record as a chip lead or equivalent technical owner on complex SoC/ASIC programs, from architecture through tape-out and post-silicon productization
- · Deep expertise in high-speed mixed-signal SoC design, including SerDes (100G+/lane), DSP datapath, analog/digital integration, and advanced CMOS process nodes (5nm, 3nm)
- · Strong understanding of the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out