# Silicon Design-for-Test (DFT) Engineer at MatX

- Company: MatX
- What the company does: We make the best chips physically possible for the large model needs of frontier labs.
- Company website: https://matx.com
- Type: Startups
- Level: Mid level
- Location: Mountain View (HQ) or Remote
- Work setup: Remote
- Pay: $160K to $275K base salary per year (USD)
- Posted: 2024-12-19
- Apply by: 2026-10-08
- Apply: https://jobs.ashbyhq.com/matx/ff6ae508-4c0e-4e36-9471-b2592eac8370
- Page: https://www.1752.vc/careers/jobs/matx-silicon-design-for-test-dft-engineer/

## About the role

Design and develop functional test solutions for SERDES PHY , covering loopback, eye diagram characterization, and margin testing. Perform DFT integration of PHY IP blocks, including boundary scan, BIST interfaces, and test mode control signals, and develop robust pattern porting flows from IP-level to SoC-level.

## What they're looking for

- Hands-on experience with DFT implementation — MBIST, at-speed scan and scan compression
- Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN)
- Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization
- Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture
- Experience with system-level DFT access — hierarchical test access, test data compression, and multi-die/chiplet DFT — is a strong plus
- Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent

Tags: Hardware