# Physical Design and Verification Engineer at Neuralink

- Company: Neuralink
- What the company does: Creating a generalized brain interface to restore autonomy to those with unmet medical needs today and unlock human potential tomorrow. Backed by Lightspeed, Sequoia and Founders Fund.
- Company website: https://neuralink.com/
- Type: Startups
- Level: Mid level
- Location: South San Francisco, California, United States
- Work setup: On-site
- Posted: 2026-11-05
- Apply by: 2026-12-20
- Apply: https://boards.greenhouse.io/neuralink/jobs/8197036003?gh_jid=8197036003&utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/neuralink-physical-design-and-verification-engineer/

## About the role

We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- BS/MS in Electrical/Computer Engineering (or equivalent) with 5+ years of physical design experience, MS preferred
- Proven full-cycle RTL-to-GDSII experience on advanced nodes (7nm/5nm/4nm/3nm or comparable)
- Hands-on hierarchical/top-level implementation on large (multi-million instance) designs
- Strong command of STA concepts (setup/hold, OCV/AOCV/POCV, MMMC) and physical verification signoff
- Proficiency with industry PnR and signoff tools (e.g., Cadence Innovus/Genus/Tempus/Voltus, Synopsys ICC2/Fusion Compiler/PrimeTime/StarRC, Siemens Calibre) and TCL scripting

Tags: Brain Interfaces Hardware

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/neuralink-physical-design-and-verification-engineer/