# Staff Technical Program Manager, ASIC at Neurophos

- Company: Neurophos
- What the company does: Neurophos develops photonic AI processing technology that focuses on hardware solutions for accelerating artificial intelligence inference by replacing traditional electronic compute elements with Optical Processing Units (OPUs). Backed by Purple Arch Ventures.
- Company website: https://neurophos.com
- Type: Startups
- Level: Senior
- Location: Austin, Texas
- Work setup: On-site
- Pay: $180K to $215K base salary per year (USD)
- Posted: 2026-09-10
- Apply by: 2026-10-25
- Apply: https://jobs.ashbyhq.com/neurophos/2759c372-ad03-4e4c-acbe-0b7ecc16ebe2
- Page: https://www.1752.vc/careers/jobs/neurophos-staff-technical-program-manager-asic/

## About the role

The Electronic IC (EIC) is the high-speed mixed-signal ASIC at the heart of our optical compute engine. It drives, reads out, and controls our photonic hardware and connects it to the rest of the system. We are looking for an experienced hardware TPM to drive the EIC program end-to-end: from architecture convergence with our chip architects, through design, verification, physical design, and tapeout at a leading-edge foundry, into post-silicon bring-up and system integration.

## What they're looking for

- BS in Electrical/Computer Engineering or equivalent (MS preferred)
- 10+ years in ASIC/SoC development , as a TPM/EPM (or equivalent lead role) on complex silicon programs
- 2+ complete silicon programs taken from architecture/specification through tapeout at a reputable foundry , with at least one carried through post-silicon bring-up to production or system integration
- Working fluency across the full silicon lifecycle: architecture, front-end design, verification, FPGA/emulation, physical design, DFT, signoff, package and substrate design, foundry manufacturing, bring-up, ATE, and reliability/qualification
- Direct experience managing foundry, IP vendor, OSAT, and design-services relationships, including tapeout logistics and mask releases
- Enough technical depth to communicate credibly with engineers across the design stack, pressure-test schedules, and understand the technical substance of the risks you are driving

Tags: Engineering