# CPU Clock Distribution and Custom Circuit Design at NUVACORE

- Company: NUVACORE
- What the company does: NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
- Company website: https://www.nuvacore.ai/
- Type: Startups (AI role)
- Level: Mid level
- Location: Austin
- Work setup: Hybrid
- Pay: $140K to $250K base salary per year (USD)
- Posted: 2026-09-21
- Apply by: 2026-11-05
- Apply: https://jobs.lever.co/nuvacore/5eaa1f33-2e9a-4d4f-9211-19eb6064a1eb
- Page: https://www.1752.vc/careers/jobs/nuvacore-cpu-clock-distribution-and-custom-circuit-design/

## About the role

As a Custom Clock Design and Distribution (CCD) Engineer, you will participate in the following : Architect and drive the end-to-end clock generation and distribution methodology using H-tree, mesh, spine, and multi-source clock-tree synthesis for high-frequency CPU cores, co-optimizing skew, insertion delay, jitter, duty-cycle distortion, and clock power.

## What they're looking for

- Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in clock design, clock distribution, and/or custom circuit design
- Hands-on transistor-level design experience with clock dividers, deskew and duty-cycle correction, clock-gating and mux cells at advanced CMOS nodes
- Proven experience constructing and analyzing low-skew, low-power clock distribution networks using H-tree, mesh, spine, and multi-source CTS for high-frequency CPUs
- Strong SPICE simulation and analysis skills, with solid grounding in device physics, RC delay, and signal integrity applied to clock-path design and verification
- Well-versed in STA and clock timing signoff including setup, hold, duty cycle closure across Functional and DFT (Design for Test) modes
- Demonstrated track record delivering clock networks and/or clocking IP through tape-out, with silicon-validated PPA — frequency, skew, jitter, and power — in high-volume products

Tags: PHYSICAL DESIGN