# CPU Custom Library and Memory Layout Lead at NUVACORE

- Company: NUVACORE
- What the company does: NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
- Company website: https://www.nuvacore.ai/
- Type: Startups (AI role)
- Level: Senior
- Location: Austin
- Work setup: Hybrid
- Pay: $20K to $300K base salary per year (USD)
- Posted: 2026-09-18
- Apply by: 2026-11-02
- Apply: https://jobs.lever.co/nuvacore/f7f773e2-cb8d-4ff1-a6df-b4d5d191ce98
- Page: https://www.1752.vc/careers/jobs/nuvacore-cpu-custom-library-and-memory-layout-lead/

## About the role

As a Custom Library and Memory Layout Lead, you will participate in the following : Lead physical layout of custom library cells (flip-flops, clock-gating cells, level shifters, AOI cells) and custom memory arrays (bit cell arrays, sense amps, decoders, register files) at advanced process nodes - own layout prototyping of critical cells.

## What they're looking for

- Hold a BS or MS degree with 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes
- Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays — bit cells, sense amps, decoders — at advanced CMOS nodes
- Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard EDA tools (e.g. Virtuoso, Calibre, StarRC)
- Strong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit PPA and variation
- Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements
- Strong communication and collaboration skills, comfortable working directly with circuit design, foundry, and CAD partner teams

Tags: PHYSICAL DESIGN