# CPU Performance Modeling (Lead & ICs) at NUVACORE

- Company: NUVACORE
- What the company does: NUVACORE builds for the stratosphere. Maximum performance. Absolute area efficiency. No compromise. A general-purpose CPU core designed to excel everywhere, from core infrastructure to advanced AI systems, including the continuous demands of agentic computing. Backed by Sequoia.
- Company website: https://www.nuvacore.ai/
- Type: Startups (AI role)
- Level: Senior
- Location: Santa Clara
- Work setup: Hybrid
- Pay: $140K to $300K base salary per year (USD)
- Posted: 2026-09-22
- Apply by: 2026-11-06
- Apply: https://jobs.lever.co/nuvacore/e858ce75-33ee-4e93-9e64-7ccc856cb01a
- Page: https://www.1752.vc/careers/jobs/nuvacore-cpu-performance-modeling-lead-and-ics/

## About the role

Design, develop and own Nuvacore’s cycle-accurate CPU performance simulator — its architecture, fidelity, and long-term roadmap — as the authoritative reference model for the design team. Experience developing trace-based and execution-driven CPU performance simulators. Lead microarchitectural exploration across all major CPU domains: frontend (fetch, decode, branch prediction), out-of-order engine (rename, dispatch, execution), and memory subsystem (caches, prefetchers, TLBs, coherence).

## What they're looking for

- MS in Computer Architecture, Computer Engineering, or related field (PhD preferred)
- 20+ years (Lead) or 8+ years (ICs) in CPU microarchitecture and/or performance engineering
- 20+ years (Lead) or 8+ years (ICs) of hands-on experience with cycle-accurate C++ CPU performance simulators (e.g. gem5 or equivalent in-house tools)
- Deep expertise in at least one of: branch prediction, fetch/decode, rename/dispatch, OOO execution, memory subsystem, or prefetchers
- Strong C++ and Python / Perl skills, ability to write and analyse assembly for microarchitectural test cases
- Proven track record driving performance from pathfinding through silicon (RTL correlation and/or post-Si debug)

Tags: ARCHITECTURE