# Senior ASIC Design Verification Engineer at Palo Alto Networks

- Company: Palo Alto Networks
- What the company does: Implement Zero Trust, Secure your Network, Cloud workloads, Hybrid Workforce, Leverage Threat Intelligence & Security Consulting. Cybersecurity Services & Education for CISO’s, Head of Infrastructure, Network Security Engineers, Cloud Architects & SOC Managers. Backed by Greylock, Sequoia and Felicis.
- Company website: https://www.paloaltonetworks.com/
- Type: Startups
- Level: Senior
- Location: Santa Clara, United States of America
- Work setup: On-site
- Posted: 2026-09-14
- Apply by: 2026-10-29
- Apply: https://paloaltonetworks.wd5.myworkdayjobs.com/en-US/panwexternalcareers/job/Santa-Clara-United-States-of-America/ASIC-Design-Verification-Engineer_JR-016294
- Page: https://www.1752.vc/careers/jobs/palo-alto-networks-senior-asic-design-verification-engineer/

## About the role

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

## What they're looking for

- Your Experience
- BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred
- Minimum 5 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production
- Expertise in SystemVerilog and UVM
- Defining test plans, including comprehensive adversarial testing
- Developing rich functional coverage models