# Sr FPGA Design Engineer (NetSec) at Palo Alto Networks

- Company: Palo Alto Networks
- What the company does: Implement Zero Trust, Secure your Network, Cloud workloads, Hybrid Workforce, Leverage Threat Intelligence & Security Consulting. Cybersecurity Services & Education for CISO’s, Head of Infrastructure, Network Security Engineers, Cloud Architects & SOC Managers. Backed by Greylock, Sequoia and Felicis.
- Company website: https://www.paloaltonetworks.com/
- Type: Startups
- Level: Senior
- Location: Office - USA - CA - Headquarters
- Work setup: On-site
- Posted: 2026-10-29
- Apply by: 2026-12-13
- Apply: https://paloaltonetworks.wd5.myworkdayjobs.com/en-US/panwexternalcareers/job/Office---USA---CA---Headquarters/Sr-FPGA-Design-Engineer--NetSec-_JR-023759?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/palo-alto-networks-sr-fpga-design-engineer-netsec/

## About the role

Join our FPGA engineering team and help deliver high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring-up, collaborating closely with cross-functional software, hardware, and verification teams. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- BS in EE, CE, or CS (MSEE or equivalent military experience preferred)
- 5+ years FPGA/CPLD development experience
- Expert SystemVerilog and Verilog RTL development skills for FPGA and CPLD architectures and is familiar with simulation tools, such as: VCS, Questa, etc. for block level verification
- Proven track record of FPGA synthesis, placement, routing, and static timing analysis (STA) closure across multi-clock domains
- Scripting proficiency (Python, C/C++, Perl, bash or tcsh)
- Demonstrated strength in: Integrating and configuring high-speed IP cores (e.g., PCIe Gen4/5/6, DMA, Ethernet MAC/PHY, memory controllers)


Source: 1752vc Careers, https://www.1752.vc/careers/jobs/palo-alto-networks-sr-fpga-design-engineer-netsec/