# Chip Design Engineer at Ricursive Intelligence

- Company: Ricursive Intelligence
- What the company does: We develop frontier AI methods to reinvent chip development, collapsing traditional design timelines, closing the loop between AI and the hardware that fuels it, and enabling a Cambrian explosion of custom silicon. Backed by Lightspeed, Sequoia and Felicis.
- Company website: https://www.ricursive.com/
- Type: Startups
- Level: Mid level
- Location: Palo Alto
- Work setup: On-site
- Posted: 2026-09-10
- Apply by: 2026-10-25
- Apply: https://jobs.ashbyhq.com/Ricursive%20Intelligence/7f7479d1-fb6a-4655-a7b0-f020fd058b9f
- Page: https://www.1752.vc/careers/jobs/ricursive-intelligence-chip-design-engineer/

## About the role

We are hiring an engineer who deeply understands every step of the flow, from synthesis through tapeout, and who has personally fought complex blocks to closure at an advanced node. Your expertise will guide the design of self-improving systems that you will then use to build real silicon. Contribute to synthesis, DFT insertion, floorplanning, PDN design, placement, CTS, routing, and all electrical, timing, and physical signoff.

## What they're looking for

- BS in Electrical Engineering, Computer Engineering, Computer Science, or a closely related technical field
- Day-one fluency in at least one production implementation and signoff stack with chip design tools and strong Tcl and Python scripting
- Track record of successful chip design and tapeout: owned closure of complex blocks, subsystems, or full chips through complete signoff in advanced technology nodes, on silicon that taped out and shipped to production
- Masters or PhD in EE, CE, CS, or a related field, with a focus on VLSI, physical design, or EDA/CAD algorithms
- Deep expertise in high-performance compute silicon (e.g., ML accelerators, CPUs, GPUs, or large SoCs), including multi-voltage domain (UPF) design and 2.5D/3D integration with bump/RDL planning
- Publications at major conferences (e.g., DAC, ICCAD, ISPD, DATE) demonstrating research strength in physical design or AI for chip design

Tags: Engineering