# Principal Engineer, Layout Design at SiTime

- Company: SiTime
- What the company does: SiTime is a leader in MEMS timing solutions, having shipped billions of units. Learn about our silicon MEMS oscillators, TCXOs, OCXOs, MEMS resonators, clock generators, jitter cleaners, clock timing, timing clock, sitm stock, and much more. Backed by NEA.
- Company website: https://www.sitime.com/
- Type: Startups
- Level: Principal and up
- Location: California, Santa Clara
- Work setup: On-site
- Posted: 2026-10-15
- Apply by: 2026-11-29
- Apply: https://job-boards.greenhouse.io/sitimecorporation/jobs/4452938009?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/sitime-principal-engineer-layout-design/

## About the role

The Senior Layout Design Engineer will lead top-chip, block-level and perform custom Analog Layout Design for CMOS and BiCMOS circuits. This role includes reviewing and coordinating work performed by offshore layout designers, training junior layout engineers and offshore contractors, contributing to the development of standard layout methodologies across sites, and helping establish processes and procedures that ensure high-quality layout design Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- BA/BS degree in Layout Design or a related field, or equivalent experience
- 15+ years of experience in layout design for analog and full-custom digital blocks
- Experience with TSMC 180nm, 65nm, 22nm process technologies
- Proficiency with layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre
- Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation

Tags: CMOS

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/sitime-principal-engineer-layout-design/