# Sr. Staff Engineer, CPU (Front-End) Verification at TensTorrent

- Company: TensTorrent
- What the company does: Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in the U.S. with offices in Austin, Texas, and Silicon Valley, and global offices in Toronto, Belgrade, Seoul, Tokyo, and Bangalore, Tenstorrent brings together...
- Company website: https://tenstorrent.com
- Type: Startups
- Level: Senior
- Location: Austin, Texas, United States; Santa Clara, California, United States
- Work setup: On-site
- Pay: $100K to $500K base salary per year (USD)
- Posted: 2026-09-04
- Apply by: 2026-10-19
- Apply: https://job-boards.greenhouse.io/tenstorrent/jobs/5229569007
- Page: https://www.1752.vc/careers/jobs/tenstorrent-sr-staff-engineer-cpu-front-end-verification/

## About the role

We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA.

## What they're looking for

- Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++
- Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking
- Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels
- Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs

Tags: RISC V: DV