# Lead SOC Design Verification (DV) Engineer at TYLsemi

- Company: TYLsemi
- What the company does: About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. Backed by Matter Venture Partners.
- Company website: https://tylsemi.ai
- Type: Startups
- Level: Senior
- Location: San Jose, CA
- Work setup: On-site
- Pay: $238K to $286K base salary per year (USD)
- Posted: 2026-09-16
- Apply by: 2026-10-31
- Apply: https://ats.rippling.com/tylsemi/jobs/bfffc267-2e86-4deb-83bf-ccecc1c4082c
- Page: https://www.1752.vc/careers/jobs/tylsemi-lead-soc-design-verification-dv-engineer/

## About the role

We are seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the verification strategy for our next-generation semiconductor products. In this role, you will lead a team of verification engineers tasked with validating highly complex, multi-million gate SoC designs.

## What they're looking for

- Technical Leadership & DV Strategy: Lead, mentor, and grow the verification team. Architect the overall verification environment, defining the standards for testbenches, automation scripts, and regression metrics
- Verification Planning: Translate architectural specifications into comprehensive verification plans. Identify edge cases, corner cases, and critical scenarios that must be stress-tested
- Environment Architecture (UVM): Own and build modular, scalable, and reusable advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM)
- Deploy AI-driven verification methodology for SoC Verification
- Advanced Verification Techniques: Deploy formal verification, assertion-based verification (SVA), and hardware/software co-verification where appropriate to accelerate bug discovery
- Signoff Discipline: Track and drive functional coverage, code coverage, and assertion metrics to absolute closure. Define and enforce the official bug-bar and criteria for pre-silicon signoff

Tags: RnD/Engineering