# Package Design Engineer at TYLsemi

- Company: TYLsemi
- What the company does: About TYLsemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. Backed by Matter Venture Partners.
- Company website: https://tylsemi.ai
- Type: Startups
- Level: Mid level
- Location: San Jose, CA
- Work setup: On-site
- Pay: $180K to $216K base salary per year (USD)
- Posted: 2026-09-09
- Apply by: 2026-10-24
- Apply: https://ats.rippling.com/tylsemi/jobs/141e3505-96d0-46ee-9def-8c6455423558
- Page: https://www.1752.vc/careers/jobs/tylsemi-package-design-engineer/

## About the role

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

## What they're looking for

- Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing
- Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR, SerDes interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques
- Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching
- Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design
- Drive DRC/DFM closure with substrate vendors, manage design review cycles through tapeout
- Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection for package robustness

Tags: RnD/Engineering