# Distinguished Engineer, SerDes Clocking at Upscale AI

- Company: Upscale AI
- What the company does: Upscale builds next-generation AI network infrastructure with scalable systems, intelligent automation, and seamless connectivity.
- Company website: https://upscale.com
- Type: Startups (AI role)
- Level: Mid level
- Location: US - Santa Clara, CA
- Work setup: On-site
- Pay: $313K to $353K base salary per year (USD)
- Posted: 2026-10-27
- Apply by: 2026-12-11
- Apply: https://jobs.lever.co/upscale-ai/51123db7-b727-4741-b8b4-1e53c515e029?utm_source=1752vc&utm_medium=careers
- Page: https://www.1752.vc/careers/jobs/upscale-ai-distinguished-engineer-serdes-clocking/

## About the role

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing. We are seeking an exceptional technical leader to define the clocking architecture for next-generation SerDes, spanning ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks. Found on 1752vc Careers, the job board for startup and VC roles.

## What they're looking for

- MS or PhD in Electrical Engineering or a related field, with extensive experience in high-performance analog and mixed-signal IC design
- Demonstrated success designing and delivering ultra-low-jitter PLLs (100 fs-class RMS integrated jitter) in advanced CMOS technologies at 5nm or below
- Deep expertise in PLL architecture and circuit design, including phase detectors or phase-frequency detectors, charge pumps where applicable, loop filters, oscillators, frequency dividers, and loop dynamics
- Strong understanding of phase noise, integrated jitter, reference spurs, loop stability, supply-induced jitter, and the impact of clock quality on high-speed SerDes performance
- Proven ability to define clocking architectures and translate stringent system-level jitter requirements into circuit-level specifications and implementation strategies
- Experience with clock distribution design and the management of coupling, skew, power integrity, and electromagnetic interactions

Tags: SerDes

Source: 1752vc Careers, https://www.1752.vc/careers/jobs/upscale-ai-distinguished-engineer-serdes-clocking/