# RTL Engineer Memory Subsystem at Velaura AI

- Company: Velaura AI
- What the company does: Backed by MVP Ventures.
- Company website: https://velaura.ai
- Type: Startups
- Level: Mid level
- Location: Santa Clara, CA
- Work setup: On-site
- Pay: $150K to $250K base salary per year (USD)
- Posted: 2026-09-16
- Apply by: 2026-10-31
- Apply: https://jobs.lever.co/velaura/d1cfb0b2-8f0b-4ba6-a3b2-78bb2aff16df
- Page: https://www.1752.vc/careers/jobs/velaura-ai-rtl-engineer-memory-subsystem/

## About the role

We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip.

## What they're looking for

- Experience designing RTL for complex digital systems, with hands-on ownership of memory subsystem blocks
- Demonstrated experience integrating a memory controller with a memory PHY, including controller-to-PHY interfaces such as DFI, initialization and training sequences, and bring-up
- Strong understanding of high-speed, low-power memory technologies such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including their protocol, timing, and power-state behavior
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
- Expert-level Verilog and SystemVerilog skills and experience with modern RTL design methodologies, including lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent
- Familiarity with performance, power, and area tradeoffs in the memory path

Tags: RTL