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Product Architectural Model Development Leader

Altera · San Jose, California, United States · On-site

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About Altera

Backed by a16z.

About the role

This role sits at the intersection of architecture, verification, software enablement, and customer enablement — the behavioral models you and your team build become the single source of truth used by architects for pathfinding and performance analysis, by verification teams for golden-reference checking, by RTL design teams as an internal product reference for intended behavior, and by software/compiler teams for early enablement, long before silicon or even RTL exists. Found on 1752vc Careers, the job board for startup and VC roles.

What they're looking for

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field (Master's or PhD preferred)
  • 15+ years of experience in silicon architecture, design, or verification, with 5+ years in a technical leadership role
  • Strong hands-on experience developing behavioral, functional, or performance models in C++, SystemC, and/or System Verilog
  • Deep understanding of FPGA or ASIC architecture fundamentals (fabric architecture, memory subsystems, interconnect, hard IP blocks)
  • Experience bridging architecture specifications into simulatable models used for verification and/or performance analysis
  • Experience using pre-silicon models to enable software, firmware, drivers, or customer development ahead of RTL or silicon availability
More about this role

Position Summary

Altera is seeking a Product Architecture Model Development Leader to drive the creation, quality, and evolution of behavioral and architectural models that represent next-generation FPGA silicon before and during RTL development.

This role sits at the intersection of architecture, verification, software enablement, and customer enablement — the behavioral models you and your team build become the single source of truth used by architects for pathfinding and performance analysis, by verification teams for golden-reference checking, by RTL design teams as an internal product reference for intended behavior, and by software/compiler teams for early enablement, long before silicon or even RTL exists. These models will also enable customers earlier in the product lifecycle through pre-silicon functional simulation, early RTL and data-flow development, and software and driver development ahead of device availability.

You will lead a team of model developers and set the technical direction for how Altera represents FPGA fabric, hard IP, and system-level behavior in executable, simulatable form.

Key Responsibilities

Technical Leadership

  • Lead a team of behavioral...

Read the full posting on Altera's site ↗

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