Backed by a16z.
About the role
As a Sr. Debug Design Verification Engineer , you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- 8+ years of experience with complex ASIC designs and/or verification
- 8+ years of experience with SystemVerilog language
- 8+ years of experience on UVM verification methodology, and formal verification method
- 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable
- Strong communication skills and the ability to work with a team spread across different geography sites
More about this role
At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry ‑ leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
As a Sr. Debug Design Verification Engineer , you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.
Pre-silicon system verification. This...
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