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About the role
Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will support timing analysis and closure activities for FPGA designs, working closely with experienced Timing, Physical Design, RTL Design, and Architecture engineers. Found on 1752vc Careers, the job board for startup and VC roles.
What they're looking for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- 1+ year of relevant experience in timing analysis, digital design, semiconductor engineering, VLSI, ASIC, FPGA, or a related technical field
- 1+ year of experience or equivalent hands-on project experience with digital logic, digital circuits, computer architecture, or integrated circuit design
- 1+ year of experience or coursework involving timing analysis, simulation, design verification, or related engineering analysis
- 1+ year of experience or coursework using Linux/Unix environments and technical scripting with Python, Tcl, Perl, or similar languages
- Foundational understanding of digital timing concepts, setup and hold timing, clocking, and semiconductor design methodologies
More about this role
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will support timing analysis and closure activities for FPGA designs, working closely with experienced Timing, Physical Design, RTL Design, and Architecture engineers.
You will gain hands-on experience with static timing analysis (STA), timing constraints, timing reports, timing optimization, and timing closure methodologies. The ideal candidate has a strong foundation in digital design and timing concepts and is interested in developing expertise in semiconductor timing analysis and advanced FPGA design...
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